The metal lines over insulators and ground planes, metal lines buried in close proximity to dielectric insulators and used for integrated circuit interconnects, and interconnection lines on interposers and printed circuit boards are in reality transmission lines. The use of coaxial interconnections through the substrate in CMOS integrated circuits can also be considered transmission lines.
The low characteristic impedance of these interconnection lines results in part from the low characteristic impedance of free space, Z0=(μ0/ε0)1/2=377 ohms, and in part from the dielectric material used for electrical insulation in the lines which has a higher dielectric permittivity than free space. Most commonly used coaxial lines have an impedance of 50 ohms or 75 ohms, as it is difficult to achieve larger values.
In the past these effects have not received much consideration in integrated circuits themselves since the signal propagation speed with oxide insulators is 15 cm/ns and switching speeds on integrated circuits the size of a centimeter have been slower than 1/15 ns or 70 ps. Switching times in CMOS circuits have been limited by the ability to switch the capacitive loads of long lines and buffers, and charge these capacitances over large voltage swings to yield a voltage step signal. Transmission line effects become important only if the switching time is of the same order as the signal propagation time.
Previously, most CMOS integrated circuit interconnections relied on the transmission of a voltage step or signal from one location to another. The switching time response or signal delay where voltage signaling is used is generally slow if the transmission line is long. Further, if two transmission lines are in close proximity to one another, the voltage swing on one line can induce a large voltage swing or noise voltage on a neighboring transmission line.
Transmission line effects and techniques for improved transmission line interconnections are described in “Current Mode Signal Interconnects and CMOS Amplifier,” Forbes et. al., U.S. Pat. No. 6,255,852, which is incorporated herein by reference. Specifically, techniques using current signaling over low impedance transmission lines, wherein the transmission fines are impedance matched, instead of voltage signaling are disclosed. Also, techniques allowing for a very fast interconnection signal response are disclosed. Additional techniques for improved methods and structures for transmission lines are disclosed in U.S. Pat. No. 6,373,740, Forbes, et al., titled “Transmission Lines for CMOS Integrated Circuits,” which is incorporated herein by reference. Specifically, forming a transmission line between electrically conductive lines and conductive planes to reduce signal delay, skew and crosstalk is disclosed.
Inductive effects on interconnection lines that are more pertinent at high speeds are a function not only of the self inductance of the interconnection lines, L, but also the mutual inductance between interconnection lines, M. FIG. 1 illustrates two adjacent interconnection lines 10A, 101B with a mutual inductance, M, between the two lines, and the calculation of the voltage (V=M di/dt) induced on an adjacent line by magnetic coupling and mutual inductance.
A noise current will be induced in an adjacent line 101B in close proximity, s=1 μm, for the whole 0.1 cm length, 1. In a system utilizing signal currents over low impedance transmission lines, the noise current will be a few percent of the signal current and the noise to signal ratio will become undesirable. Reduction of the noise current, however, is desirable.
In general, it can be shown that if the line is impedance matched, the signal to noise ratio due to inductive coupling is of the order (L/M)(trise/tprop), where trise is the rise time of the current waveform and tprop is the propagation time down the line. Therefore, techniques are needed which will minimize the mutual inductance between lines and improve the signal-to-noise ratio on high speed interconnection lines in integrated circuits.